A low-power switched-current algorithmic A/D converter
نویسندگان
چکیده
This paper reports the development of a low-power switchedcurrent algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter uses modified SI type current copiers to reduce the overall area and power consumption. The analog portion of the converter occupies only 0.35mm area in 3μm CMOS technology. The simulation results show that the converter provides 10 bits resolution with a conversion rate of 61kHz, while dissipating only 1mW power from a single 5V supply.
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